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INTEGRATED CIRCUITS
74LV595 8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
Product specification IC24 Data Handbook 1998 Apr 20
Philips Semiconductors
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
FEATURES
* Optimized for Low Voltage applications: 1.0V to 3.6V * Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V * Typical VOLP (output ground bounce) < 0.8V at VCC = 3.3V, * Typical VOHV (output VOH undershoot) > 2V at VCC = 3.3V, * 8-bit serial input * 8-bit serial or parallel output * Storage register with 3-State outputs * Shift register with direct clear * Output capability:
- parallel outputs; bus driver - serial output; standard Tamb = 25C Tamb = 25C
APPLICATIONS
* Serial-to-parallel data conversion * Remote control holding register
DESCRIPTION
The 74LV595 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT595. The74LV595 is an 8-stage serial shift register with a storage register and 3-State outputs. The shift register and storage register have separate clocks. Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial standard output (Q7') all for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-State bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
* ICC category: MSI
QUICK REFERENCE DATA
GND = 0V; Tamb = 25C; tr =tf v2.5 ns SYMBOL PARAMETER Propagation delay SHCP to Q7' STCP to Q7' MR to Q7' Maximum clock frequency SHCP, STCP Input capacitance Power dissipation capacitance per gate VCC = 3.3V Notes 1 and 2 CONDITIONS CL = 15pF VCC= 3.3V TYPICAL 15 16 14 77 3.5 115 UNIT
tPHL/tPLH fmax CI CPD
ns
MHz pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD VCC2 x fi ) (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. (CL 2. The condition is VI = GND to VCC.
ORDERING AND PACKAGE INFORMATION
PACKAGES 16-Pin Plastic DIL 16-Pin Plastic SO 16-Pin Plastic SSOP Type II 16-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +125C -40C to +125C -40C to +125C -40C to +125C OUTSIDE NORTH AMERICA 74LV595 N 74LV595 D 74LV595 DB 74LV595 PW NORTH AMERICA 74LV595 N 74LV595 D 74LV595 DB 74LV595PW DH PKG. DWG. # SOT38-4 SOT109-1 SOT338-1 SOT403-1
1998 Apr 20
2
853-1987 19255
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
PIN DESCRIPTION
PIN NUMBER 15, 1, 2, 3, 4, 5, 6, 7 8 9 10 11 12 13 14 16 SYMBOL Q0 to Q7 GND Q7' MR SHCP STCP OE DS VCC FUNCTION Parallel data output Ground (0V) Serial data output Master reset (active LOW) Shift register clock input Storage register clock input Output enable input (active LOW) Serial data input Positive supply voltage
PIN CONFIGURATION
Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 2 3 4 5 6 7
16 VCC 15 Q0 14 DS 13 OE 12 STCP 11 SHCP 10 MR 9 Q7'
GND 8
SV00720
FUNCTION TABLE
INPUTS SHCP X X X STCP X X X OE L L H L MR L L L H DS X X X H OUTPUTS FUNCTION Q7' L L L Q6' Qn NC L Z NC A LOW level on MR only affects the shift registers Empty shift register loaded into storage register Shift register clear. Parallel outputs in high-impedance OFF-states Logic high level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6') appears on the serial output (Q7') Contents of shift register stages (internal Qn') are transferred to the storage register and parallel output stages Contents of shift register shifted through. Previous contents of the shift register are transferred to the storage register and the parallel output stages
X
L
H
X
NC
Qn'
L
H
X
Q6'
Qn'
H = HIGH voltage level L = LOW voltage level X = Don't care Z = High impedance OFF-state NC= No change = LOW-to-HIGH clock transition = HIGH-to-LOW transition
1998 Apr 20
3
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
LOGIC SYMBOL
11 12
FUNCTIONAL DIAGRAM
SHCP
STCP Q7' Q0 Q1 Q2 9 15 10 1 2 14 11
DS SHCP MR 8-STAGE SHIFT REGISTER Q7'
9
STCP 14 DS Q3 Q4 Q5 Q6 Q7 MR OE 3 4 5 6 7 15 13 OE 12
8-BIT STORAGE REGISTER
3-STATE OUTPUTS Q0 1 Q1 2 Q2 3 Q3 4 Q4 5 Q5 6 Q6 7 Q7
10
13
SV00723
SV00725
LOGIC SYMBOL (IEEE/IEC)
13 12 10 11 R C1/ SRG8
EN3 C2
14
1D
2D
3
15 1 2 3 4 5 6 7 9
SV00724
1998 Apr 20
4
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
LOGIC DIAGRAM
STAGE 0 DS D Q D
STAGES 1 to 6 Q
STAGE 7 D Q Q7'
FFO CP R SHCP MR
FF7 CP R
D
Q
D
Q
LATCH CP STCP OE
LATCH CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SV00721
TIMING DIAGRAM
SHCP
DS
STCP
MR
OE
Q0
Z-state
Q1
Z-state
Z-state Q6
Q7
Z-state
Q7'
SV00726
1998 Apr 20
5
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb tr, tf Input voltage Output voltage Operating ambient temperature range in free air Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V PARAMETER DC supply voltage CONDITIONS See Note1 MIN 1.0 0 0 -40 -40 - - - - - - TYP. 3.3 - - MAX 3.6 VCC VCC +85 +125 500 200 100 UNIT V V V C ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC =3.6V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK IOK IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current - standard outputs - bus driver outputs DC VCC or GND current for types with -standard outputs -bus driver outputs Storage temperature range Power dissipation per package -plastic DIL -plastic mini-pack (SO) -plastic shrink mini-pack (SSOP and TSSOP) for temperature range: -40 to +125C above +70C derate linearly with 12mW/K above +70C derate linearly with 8 mW/K above +60C derate linearly with 5.5 mW/K VI < -0.5 or VI > VCC + 0.5V VO < -0.5 or VO > VCC + 0.5V -0.5V < VO < VCC + 0.5V CONDITIONS RATING -0.5 to +4.6 20 50 25 35 50 70 -65 to +150 750 500 400 UNIT V mA mA mA
mA C mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VIH HIGH level Input voltage VCC = 1.2V VCC = 2.0V VCC = 2.7 to 3.6V VIL LOW level Input voltage VCC = 1.2V VCC = 2.0V VCC = 2.7 to 3.6V VCC = 1.2V; VI = VIH or VIL; -IO = 100A VOH HIGH level output voltage; all outputs HIGH level output voltage; STANDARD outputs VCC = 2.0V; VI = VIH or VIL; -IO = 100A VCC = 2.7V; VI = VIH or VIL; -IO = 100A VCC = 3.0V; VI = VIH or VIL; -IO = 100A VCC = 3.0V;VI = VIH or VIL; -IO = 6mA 1.8 2.5 2.8 2.40 1.2 2.0 2.7 3.0 2.82 1.8 2.5 2.8 2.20 V V 0.9 1.4 2.0 0.3 0.6 0.8 -40C to +85C TYP1 MAX -40C to +125C MIN 0.9 1.4 2.0 0.3 0.6 0.8 V V MAX UNIT
VOH
1998 Apr 20
6
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
DC CHARACTERISTICS (Continued)
Over recommended operating conditions voltages are referenced to GND (ground = 0V) SYMBOL PARAMETER HIGH level output voltage; BUS driver outputs TEST CONDITIONS LIMITS -40C to +85C 2.40 2.82 0 0 0 0 0.25 0.2 0.2 0.2 0.40 0.2 0.2 0.2 0.50 V V -40C to +125C 2.20 UNIT
VOH
VCC = 3.0V;VI = VIH or VIL; -IO = 8mA VCC = 1.2V; VI = VIH or VIL; IO = 100A VCC = 2.0V; VI = VIH or VIL; IO = 100A VCC = 2.7V; VI = VIH or VIL; IO = 100A VCC = 3.0V;VI = VIH or VIL; IO = 100A
V
VOL
LOW level output voltage; all outputs LOW level output voltage; STANDARD outputs LOW level output voltage; BUS driver outputs Input leakage current 3-State output OFF-state current Quiescent supply current; MSI Additional quiescent supply current per input
VOL
VCC = 3.0V;VI = VIH or VIL; IO = 6mA
VOL II IOZ ICC ICC
VCC = 3.0V;VI = VIH or VIL; IO = 8mA VCC = 3.6V; VI = VCC or GND VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC -0.6V
0.20
0.40 1.0 5 20.0 500
0.50 1.0 10 160 850
V A A A A
NOTE: 1. All typical values are measured at Tamb = 25C.
AC CHARACTERISTICS
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER WAVEFORM CONDITION VCC(V) 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 MIN - - - - - - - - - - - - - - - - - - - - LIMITS -40 to +85 C TYP1 95 32 24 182 100 34 25 192 85 29 21 162 85 29 21 162 65 24 18 142 MAX - 61 45 36 - 65 48 38 - 56 41 33 - 56 41 33 - 40 32 26 LIMITS -40 to +125 C MIN - - - - - - - - - - - - - - - - - - - - MAX - 75 55 44 - 77 56 45 - 66 49 33 - 66 49 39 - 49 37 30 UNIT
tPHL/tPLH
Propagation delay g y SHCP to Q7'
Figure 1
ns
tPHL/tPLH
Propagation delay g y STCP to Qn
Figure 2
ns
tPHL
Propagation delay g y MR to Q7'
Figure 5
ns
tPZH/tPZL
3-State t t 3 St t output enable time OE to Qn 3-State t t 3 St t output disable time OE to Qn
Figure 3
ns
tPHZ/tPLZ
Figure 3
ns
1998 Apr 20
7
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
AC CHARACTERISTICS (Continued)
GND = 0V; tr = tf 2.5ns; CL = 50pF; RL = 1K SYMBOL PARAMETER CONDITION VCC(V) 2.0 2.7 3.0 to 3.6 2.0 2.7 3.0 to 3.6 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 1.2 2.0 2.7 3.0 to 3.6 2.0 2.7 3.0 to 3.6 MIN 34 25 20 34 25 20 34 25 20 - 26 19 15 - 26 19 15 - 5 5 5 - 5 5 5 14 19 24 LIMITS -40 to +85 C TYP1 10 8 62 7 5 42 10 8 62 40 14 10 82 40 14 10 82 -10 -4 -3 -22 -35 -12 -9 -72 40 58 702 MAX - - - - - - - - - - - - - - - - - - - - - - - - - - - - LIMITS -40 to +125 C MIN 41 30 24 41 30 24 41 30 24 - 31 23 18 - 31 23 18 - 5 5 5 - 5 5 5 12 16 20 MAX - - - - - - - - - - - - - - - - - - - - - - - - - - - -
WAVEFORM
UNIT
tW
Shift clock pulse width HIGH or LOW Storage clock pulse width HIGH or LOW Master reset pulse width LOW
Figure 1
ns
tW
Figure 2
ns
tW
Figure 5
ns
tsu
Set-up time DS to SHCP
Figure 4
ns
tsu
Set-up time SHCP to STCP
Figure 2
ns
th
Hold time DS to SHCP
Figure 4
ns
trem
Removal time MR to SHCP Maximum clock pulse frequency SHCP or STCP
Figure 5
ns
fmax
Figure 1, 2
MHz
NOTES: 1. Unless otherwise stated, all typical values are at Tamb = 25C. 2. Typical value measured at VCC = 3.3V.
1998 Apr 20
8
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V VM = 0.5 * VCC at VCC t 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC 2.7V VX = VOL + 0.1VCC at VCC < 2.7V VY = VOH - 0.3V at VCCw 2.7V VY = VOH - 0.1VCC at VCC < 2.7V
VI OE INPUT GND tPLZ VCC OUTPUT LOW-to-OFF OFF-to-LOW VOL 1/fmax VI CP INPUT GND VM tW tPHL VOH Qn OUTPUT VOL VM tPLH VOH OUTPUT HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled tPHZ VY VM VX tPZH tPZL VM
VM
SV00344
Figure 3. 3-State enable and disable times for input OE.
SV00718
Figure 1. Clock (SHCP) to output (Q7'), propagation delays, the shift clock pulse width and the maximum shift clock frequency.
VI SHCP INPUT GND VI SHCP INPUT GND tsu VI STCP INPUT GND VM tW tPLH VOH Qn OUTPUT VOL VM tPHL 1/fmax VM VM
t su
t su
th VI DS INPUT
th
GND
vOH
Q7' OUTPUT VOL
Figure 4. Data set-up and hold times for the data input (DS).
SV00727
Figure 2. Storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time.
1998 Apr 20
9
IIIIIIII IIII IIIIIIII IIII IIIIIIII IIII
VM VM
SV00722
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
AC WAVEFORMS (Continued)
VM = 1.5V at VCC w 2.7V VM = 0.5 * VCC at VCC t 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC 2.7V VX = VOL + 0.1VCC at VCC < 2.7V VY = VOH - 0.3V at VCCw 2.7V VY = VOH - 0.1VCC at VCC < 2.7V
TEST CIRCUIT
VCC S1 2 * VCC Open GND
VI PULSE GENERATOR RT D.U.T.
VO
RL = 1k
50pF
CL
RL = 1k
Test Circuit for switching times
VI MR INPUT GND tW trem VI SHCP INPUT GND VOH Q7' OUTPUT VOL VM VM VM
DEFINITIONS
RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators.
SWITCH POSITION
TEST tPLH/tPHL tPLZ/tPZL S1 Open 2 < VCC
GND
VCC < 2.7V 2.7-3.6V
VI VCC 2.7V
tPHL
tPHZ/tPZH
SV00895
Figure 6. Load circuitry for switching times.
SV00728
Figure 5. Master reset (MR) pulse width, the master reset to output (Q7') propagation delay and the master reset to shift clock (SHCP) removal time.
1998 Apr 20
10
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
1998 Apr 20
11
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1998 Apr 20
12
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
1998 Apr 20
13
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
1998 Apr 20
14
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
NOTES
1998 Apr 20
15
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift register with output latches (3-State)
74LV595
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-04455
Philips Semiconductors
1998 Apr 20 16

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